Isil Dillig

Registered user since Thu 10 Apr 2014

Name: Isil Dillig

Bio: I am an assistant professor at the computer science department of the University of Texas at Austin. My main research interests are program analysis and verification, formal methods, and automated logical reasoning. The overarching goal of my research is to make software systems more reliable, secure, and easier to build in a robust way.

I obtained all my degrees (BS, MS, PhD) at Stanford University , where my PhD advisor was Alex Aiken . Prior to joining UT Austin, I worked as a researcher at Microsoft Research Cambridge (2013-2014) and as an assitant professor at the College of William & Mary (2012-2013).

Research Interests: my main research interests are static program analysis/verification and automated logical reasoning. I am interested in developing tools and novel techniques to make software systems more secure and reliable. In particular, my research focuses on automatically proving the absence of certain classes of errors (such as memory safety errors, assertion failures, etc.) in software.

More specifically, my research on static analysis tackles the challenge of designing algorithms that are both sound (i.e., never miss any potential program errors) as well as precise (i.e., do not report a lot of false alarms) and scalable (i.e., work on large programs). Towards this goal, I have worked on a variety of topics including pointer and data structure analysis, loop invariant generation, path-sensitive analysis, and compositional reasoning. On the automated logical reasoning side, I have worked on decision procedures for logical satisfiability, constraint simplification, and abductive inference. I am also interested in program synthesis, applications of static analysis in security, and program optimization techniques.

Country: Turkey

Affiliation: University of Texas, Austin

Personal website:

Research interests: Static program analysis/verification and automated logical reasoning


PLDI 2016Author of Cartesian Hoare Logic for Verifying k-Safety Properties within the Research Papers-track
Session Chair of Verification I (part of Research Papers)
Author of Synthesizing Transformations on Hierarchically Structured Data within the Research Papers-track
Committee Member in Program Committee
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